1. Field of the Invention
Example non-limiting embodiments of the present invention relate generally to a wafer level package, and more particularly, to a method for forming a redistribution interconnection metal layer.
2. Description of the Related Art
Wafer level packaging may proceed with a semiconductor chip having a semiconductor device which may not be separated from a wafer.
In wafer level packaging, a redistribution interconnection metal layer may be provided on an electrode pad to support external connection electrodes that may be disposed on the surface of the semiconductor substrate. FIGS. 1A through 1F show a conventional method that may be implemented to provide a redistribution interconnection metal layer in a wafer level package.
Referring to FIG. 1A, a first insulating layer 20 may be provided on a passivation layer 13 that may be provided on a semiconductor substrate 10. The first insulating layer 20 and the passivation layer 13 may be patterned to expose an electrode pad 11 that may be provided on the semiconductor substrate 10.
Referring to FIG. 1B, a seed metal layer 30 may be provided on the first insulating layer 20 and the exposed portion of the electrode pad 11.
Referring to FIG. 1C, a photoresist pattern (not shown) may be provided on the seed metal layer 30, and a redistribution interconnection metal layer 40 may be provided on the portions of the seed metal layer 30 that may be exposed through the photoresist pattern. The redistribution interconnection metal layer 40 may be formed by electrical plating, for example. The redistribution interconnection metal layer 40 may be provided on portions of the seed metal layer 30, which may be provided on the entire surface of the semiconductor substrate.
Referring to FIG. 1D, unwanted portions of the seed metal layer 30 may be removed via a wet etching process using the redistribution interconnection metal layer 40 as a mask.
Referring to FIG. 1E, a second insulating layer 50 may be provided on the redistribution interconnection metal layer 40. The second insulating layer 50 may be patterned to expose a portion of the redistribution interconnection metal layer 40.
Referring to FIG. 1F, a connection electrode 60 may be provided on the exposed portion of the redistribution interconnection metal layer 40.
Although the conventional art is generally thought to provide acceptable results, it is not without shortcomings. For example, during wet etching of the seed metal layer 30, an exposed side portion of the redistribution interconnection metal layer 40 may be etched and undercut.
FIG. 2 shows an undercut that may be formed beneath the redistribution interconnection metal layer 40. Here, the redistribution interconnection metal layer 40 may include a Cu layer 41, a Ni layer 43 and an Au layer 45, for example. The wet etching performed on the seed metal layer 30 may be an isotropic etch, for example. Thus, the undercut may occur on the redistribution interconnection metal layer 40 when the seed metal layer 30 is removed. The undercut may cause the redistribution interconnection metal layer 40 to separate from the substrate when the second insulating layer 50 (which may be fabricated from polyimide, for example) is provided through spin coating process, for example. Further, air, which may be confined in the undercut of the redistribution interconnection metal layer 40, may expand and form bubbles when the second insulating layer 50 is provided. The bubbles may raise the second insulating layer 50 from the redistribution interconnection metal layer 40.